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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/24/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.all;

ENTITY par2ser_32bit IS
	PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
			reset			: IN  STD_LOGIC;	-- Reset input
			enable			: IN  STD_LOGIC;	-- Enable
			input			: IN  STD_LOGIC_VECTOR (31 DOWNTO 0);	-- Input
      		q	 			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)  	-- Output
			);
END par2ser_32bit;

ARCHITECTURE behav OF par2ser_32bit IS
	SIGNAL mux_select : STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL completed  : STD_LOGIC;
BEGIN
	PROCESS (clock, reset, enable, completed)
	BEGIN
		IF reset = '1' THEN
	 	    mux_select <= "0000";
			completed <= '0';
		ELSIF enable = '1' THEN
			IF completed = '0' THEN
				IF (clock'event AND clock = '1') THEN
					CASE mux_select IS
						WHEN "0000" => 
							q <= input(3 DOWNTO 0);
							mux_select <= "0001";
						WHEN "0001" => 
							q <= input(7 DOWNTO 4);
							mux_select <= "0010";
						WHEN "0010" => 
							q <= input(11 DOWNTO 8);
							mux_select <= "0011";
						WHEN "0011" => 
							q <= input(15 DOWNTO 12);
							mux_select <= "0100";
						WHEN "0100" => 
							q <= input(19 DOWNTO 16);
							mux_select <= "0101";
						WHEN "0101" => 
							q <= input(23 DOWNTO 20);
							mux_select <= "0110";
						WHEN "0110" => 
							q <= input(27 DOWNTO 24);
							mux_select <= "0111";
						WHEN "0111" => 
							q <= input(31 DOWNTO 28);
							mux_select <= "1000";
						WHEN OTHERS =>
							completed <= '1';
					END CASE;
			    END IF;	
			ELSE
				q <= "0000"; -- Completed!
				completed <= '1';
			END IF;		
		END IF;		
	END PROCESS;
END behav;
